1. Field of the Invention
The present invention relates to a method of forming a multilayer structure of wirings, in particular, of a semiconductor device.
2. Description of the Related Art
Presently, there is a demand of reducing a semiconductor element in size, and accordingly, there is a demand of downsizing a contact hole and a wiring layer. FIGS. 10A to 10D and 11A to 11D illustrate conventional and general methods of forming a multi-layer structure of wiring patterns.
That is, a resist pattern 103 for defining a contact hole 102 (FIG. 10B) is formed at a predetermined position of an interlayer insulating film 101 as shown in FIG. 10A. With use of this resist pattern as a mask, a contact hole 102 is formed in the interlayer insulating film 101 as shown in FIG. 10B. After removing the resist pattern 103, a wiring metal e.g. aluminum is deposited on the entire surface such that the wiring metal layer 104 and the underlying wiring layer 105 are rendered conductive. Subsequently, a resist pattern 106 having a predetermined pattern is formed on the wiring metal layer 104. With use of this resist pattern 106 as a mask, the wiring metal layer 104 is etched, thus forming a wiring layer 107.
However, the above-described conventional technique entails the problems of a low mask alignment accuracy at the time of actual processing, and the downsizing of designing margin is difficult. Further, this technique requires a step of widening the top opening portion of the contact hole 102 as shown in FIG. 10B for the purpose of sufficiently filling the contact hole with the wiring metal. Further, as the diameter of the contact hole is reduced, the contact hole is not fully filled with the wiring metal due to the over-bump portion of the wiring metal formed in the periphery of the opening portion of the contact hole, thus creating a void in the contact hole. As a result, the conduction between the wiring metal layer 104 and the underlying wiring layer 105 may not be achieved, thus degrading the electrical characteristics and the quality of the product semiconductor device. In order to solve this drawback, there is proposed a technique of depositing a metal at a high temperature, or a technique of depositing a metal at a standard temperature and then melting the metal layer. However, with these techniques, the mask alignment mark is covered by melted metal, and therefore it is difficult to find the mask alignment mark during a patterning operation of the resist on the metal layer, which takes places later, and in the worst case, the mask alignment cannot be found.
In another conventional method illustrated in FIGS. 11A to 11D, a pattern of a contact hole (FIG. 11A) is defined on the interlayer insulating film 201 using resist pattern 203 with use of the resist pattern 203 as a mask, the interlayer insulating film 201 is etched to a depth which equals to the length of a contact hole in the depth direction formed later. The line 202 denotes the center of a predetermined contact hole forming position. In the actual production step, an alignment mark on a semiconductor substrate is used as a line denoting the center of the contact hole forming position. After removing resist pattern 203, resist pattern 205 is formed on the interlayer insulating film 201 so as to define a pattern of a groove for an overlying wiring layer. In this case, the resist pattern may be displaced from a predetermined portion as shown in FIG. 11B. With use of this resist pattern as a mask, the interlayer insulating film 201 is further etched so that a through-hole is formed in the interlayer insulating film 201, as shown in FIG. 11C. The through-hole includes the groove 206 for the overlying wiring layer and contact hole 204 continuous to the wiring layer groove 206, and passes therethrough to an underlying wiring layer 207. The length of the further etched portion in the depth direction equals to the length of the wiring layer groove in the depth direction. After removing the resist pattern 205, a wiring metal layer 208 is deposited such that the conduction between the metal layer 208 and the underlying wiring layer 207 are rendered conductive (FIG. 11C). Then, the wiring metal layer 208 is melted and allowed to flow into the wiring layer groove 206 and the contact hole 204, and polishing is carried out. Thus, a conductive layer 209 for contact and a wiring layer 300 are formed in the interlayer insulation film 201, as shown in FIG. 11D.
The forming method illustrated in FIGS. 11A to 11D has been proposed so as to solve the problems with the method shown in FIGS. 10A to 10D. With this forming method, however, the patterning of the resist layer must be carried out two times: one for forming a contact hole and another one for forming a wiring layer groove. Therefore, in consideration of a mask alignment error, it is necessary to design a contact hole which is smaller than the width of the wiring layer. However, in the case where a contact hole smaller than the width of the wiring layer is designed, a step portion is created between the contact hole and the wring layer groove. As a result, during the deposition of the wiring metal layer or in the metal melting step for filling the groove with wiring metal, the problem of the contact hole being not filled completely with the wiring metal, may occur in some cases. Further, it is necessary to form a fine wiring layer resist pattern on the step portion in which the pattern of the contact hole is formed. In the case where the wiring layer resist pattern is displaced from the position where it should originally be formed, a part of the resist enters the contact hole as shown in FIG. 11B, and in this case, that part of the resist remains in the bottom portion of the contact hole. Further, due to the resist alignment error i.e. a resist misalignment, the wiring layer groove and the contact hole are formed in a different position from where it is designed.
As described above, with the conventional wiring layer forming method, it is difficult to downsize the wiring layer groove or contact hole, or to avoid an error in the resist mask alignment. Further, even if they are reduced in size, the contact hole is not filled completely with metal during the deposition of wiring metal, raising the problem of degrading the electrical characteristics and quality of the product. Furthermore, it is necessary to form a fine wiring layer groove on the step portion in which the pattern of the contact hole is formed, or some of the resist may remain in the bottom portion of the contact hole.